SH7201 Datasheet, PDF (300/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 9 Bus State Controller (BSC)
Table 9.14 SDITR Set Value Correspondence Table (Single Read Timing)
Figure
Figure 9.36
Figure 9.37
Figure 9.38
DRAS
010
000
000
DRCD
00
01
01
DPCG
001
001
001
DCL
010
010
011
Single read
CKIO
SDRAM command
ACT RD DSL PRA DSL
Data bus
d
DRCD
(ACT-RD)
DCL
(RD-d)
DPCG
(PRA-next)
DRAS
(ACT-PRA)
ACT: Row and bank activation command
RD: Read command
PRA: Precharge-all command
Figure 9.36 Single Read Timing Example 1
Rev. 2.00 Sep. 07, 2007 Page 272 of 1164
REJ09B0321-0200