SH7201 Datasheet, PDF (289/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 9 Bus State Controller (BSC)
(10) Mode Register Setting
Writing to the SDRAMm mode register (SDmMOD) causes mode register set commands and
extended mode register set commands to be issued to the various channels. Settings to the
SDRAMm mode register (SDmMOD) should be made individually for each channel.
Figure 9.23 shows the operation timing for mode register setting.
Mode register
setting cycle
Extended mode register
setting cycle
CKIO
SDRAM command
MRS DSL DSL
EMRS DSL DSL
3 cycles (fixed)
3 cycles (fixed)
DSL: Deselect command
MRS: Mode register set command
EMRS: Extended mode register set command
Figure 9.23 Operation Timing for Mode Register Setting
(11) Clock Stop Control Signal
SDRAMC outputs a clock stop control signal (CLKSTOP). CLKSTOP can be enabled or disabled
using the DCKSEN bit in the SDRAM clock stop control signal setting register (SDCKSCNT).
The CLKSTOP signal remains low level when the clock stop control signal is disabled.
When clock stop control signal is enabled, the CLKSTOP and CKIO signals operate in
conjunction with transition to and recovery from deep-power-down mode.
During a transition to deep-power-down mode, the CLKSTOP signal goes high after the deep-
power-down entry command is issued. During a recovery from deep-power-down mode, the
CLKSTOP signal goes low and a deep-power-down exit command is issued when the clearing of
the DDPD bit to 0 is accepted by SDRAMC and the CKIO starts operation.
DCKSC, the period between the change of CLKSTOP along with CKIO and the issuance of deep
power-down entry or exit command, can be set by the SDRAM clock stop control signal setting
register.
Rev. 2.00 Sep. 07, 2007 Page 261 of 1164
REJ09B0321-0200