SH7201 Datasheet, PDF (497/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.4.4 Cascaded Operation
In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit
counter.
This function works by counting the channel 1 counter clock upon overflow/underflow of
TCNT_2 as set in bits TPSC0 to TPSC2 in TCR.
Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.
Table 12.44 shows the register combinations used in cascaded operation.
Note: When phase counting mode is set for channel 1, the counter clock setting is invalid and the
counters operates independently in phase counting mode.
Table 12.44 Cascaded Combinations
Combination
Channels 1 and 2
Upper 16 Bits
TCNT_1
Lower 16 Bits
TCNT_2
For simultaneous input capture of TCNT_1 and TCNT_2 during cascaded operation, additional
input capture input pins can be specified by the input capture control register (TICCR). For input
capture in cascade connection, refer to section 12.7.22, Simultaneous Capture of TCNT_1 and
TCNT_2 in Cascade Connection.
Table 12.45 show the TICCR setting and input capture input pins.
Table 12.45 TICCR Setting and Input Capture Input Pins
Target Input Capture
Input capture from TCNT_1 to
TGRA_1
Input capture from TCNT_1 to
TGRB_1
Input capture from TCNT_2 to
TGRA_2
Input capture from TCNT_2 to
TGRB_2
TICCR Setting
I2AE bit = 0 (initial value)
I2AE bit = 1
I2BE bit = 0 (initial value)
I2BE bit = 1
I1AE bit = 0 (initial value)
I1AE bit = 1
I1BE bit = 0 (initial value)
I1BE bit = 1
Input Capture Input Pins
TIOC1A
TIOC1A, TIOC2A
TIOC1B
TIOC1B, TIOC2B
TIOC2A
TIOC2A, TIOC1A
TIOC2B
TIOC2B, TIOC1B
Rev. 2.00 Sep. 07, 2007 Page 469 of 1164
REJ09B0321-0200