SH7201 Datasheet, PDF (190/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 7 User Break Controller (UBC)
Figure 7.1 shows a block diagram of the UBC.
Access
control
Internal bus
(I bus)
IDB IAB
CPU bus
(C bus)
MDB MAB FAB
Access
comparator
Address
comparator
Data
comparator
Channel 0
Access
comparator
Address
comparator
Data
comparator
Channel 1
Control
Internaal bus
(I bus)
BBR_0
BAR_0
BAMR_0
BDR_0
BDMR_0
BBR_1
BAR_1
BAMR_1
BDR_1
BDMR_1
BRCR
[Legend]
BBR: Break bus cycle register
BAR: Break address register
BAMR: Break address mask register
User break request
UBCTRG pin output
BDR: Break data register
BDMR: Break data mask register
BRCR: Break control register
Figure 7.1 Block Diagram of UBC
Rev. 2.00 Sep. 07, 2007 Page 162 of 1164
REJ09B0321-0200