SH7201 Datasheet, PDF (17/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

12.3.28 Timer Interrupt Skipping Counter (TITCNT)....................................................... 450
12.3.29 Timer Buffer Transfer Set Register (TBTER) ...................................................... 451
12.3.30 Timer Dead Time Enable Register (TDER).......................................................... 453
12.3.31 Timer Waveform Control Register (TWCR) ........................................................ 454
12.3.32 Bus Master Interface............................................................................................. 455
12.4 Operation ........................................................................................................................... 456
12.4.1 Basic Functions..................................................................................................... 456
12.4.2 Synchronous Operation......................................................................................... 462
12.4.3 Buffer Operation ................................................................................................... 464
12.4.4 Cascaded Operation .............................................................................................. 469
12.4.5 PWM Modes ......................................................................................................... 474
12.4.6 Phase Counting Mode........................................................................................... 479
12.4.7 Reset-Synchronized PWM Mode.......................................................................... 486
12.4.8 Complementary PWM Mode................................................................................ 489
12.4.9 A/D Converter Start Request Delaying Function.................................................. 525
12.4.10 External Pulse Width Measurement...................................................................... 529
12.4.11 Dead Time Compensation..................................................................................... 530
12.4.12 TCNT Capture at Crest and/or Trough in Complementary PWM Operation ....... 532
12.5 Interrupt Sources................................................................................................................ 533
12.5.1 Interrupt Sources and Priorities ............................................................................ 533
12.5.2 DMAC Activation................................................................................................. 535
12.5.3 A/D Converter Activation..................................................................................... 535
12.6 Operation Timing............................................................................................................... 537
12.6.1 Input/Output Timing ............................................................................................. 537
12.6.2 Interrupt Signal Timing......................................................................................... 544
12.7 Usage Notes ....................................................................................................................... 548
12.7.1 Module Standby Mode Setting ............................................................................. 548
12.7.2 Input Clock Restrictions ....................................................................................... 548
12.7.3 Caution on Period Setting ..................................................................................... 549
12.7.4 Contention between TCNT Write and Clear Operations...................................... 550
12.7.5 Contention between TCNT Write and Increment Operations............................... 550
12.7.6 Contention between TGR Write and Compare Match .......................................... 551
12.7.7 Contention between Buffer Register Write and Compare Match ......................... 552
12.7.8 Contention between Buffer Register Write and TCNT Clear ............................... 553
12.7.9 Contention between TGR Read and Input Capture............................................... 554
12.7.10 Contention between TGR Write and Input Capture.............................................. 555
12.7.11 Contention between Buffer Register Write and Input Capture ............................. 556
12.7.12 TCNT_2 Write and Overflow/Underflow Contention in Cascade Connection .... 556
12.7.13 Counter Value during Complementary PWM Mode Stop .................................... 558
12.7.14 Buffer Operation Setting in Complementary PWM Mode ................................... 558
Rev. 2.00 Sep. 07, 2007 Page xvii of xxviii