SH7201 Datasheet, PDF (290/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 9 Bus State Controller (BSC)
Figures 9.24 and 9.25 show the operation timing of the clock stop control signal.
Deep-power-down mode
CKIO
SDRAM command
DPD
SDCKE
CLKSTOP
(internal signal)
DCKSC
DDPDST bit value changes to 0
DPD: Deep-power-down entry command
Figure 9.24 Clock Stop Control Signal Operation Timing
(Transition to Deep-Power-Down Mode)
Deep-power-down mode
CKIO
SDRAM command
SDCKE
DPDX
CLKSTOP
(internal signal)
DCKSC
DDPD bit cleared to 0
DDPDST bit value changes to 1
DDPDST bit value changes to 0
DPDX: Deep-power-down exit command
Figure 9.25 Clock Stop Control Signal Operation Timing
(Recovery from Deep-Power-Down Mode)
Rev. 2.00 Sep. 07, 2007 Page 262 of 1164
REJ09B0321-0200