SH7201 Datasheet, PDF (867/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 19 Controller Area Network (RCAN-ET)
19.4.5 Interrupt Mask Register (IMR)
The interrupt mask register is a 16 bit register that protects all corresponding interrupts in the
Interrupt Request Register (IRR) from generating an output signal on the IRQ. An interrupt
request is masked if the corresponding bit position is set to '1'. This register can be read or written
at any time. The IMR directly controls the generation of IRQ, but does not prevent the setting of
the corresponding bit in the IRR.
• IMR (Address = H'00A)
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
IMR15 IMR14 IMR13 IMR12 IMR11 IMR10 IMR9 IMR8 IMR7 IMR6 IMR5 IMR4 IMR3 IMR2 IMR1 IMR0
Initial value: 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit 15 to 0: Maskable interrupt sources corresponding to IRR[15:0] respectively. When a bit is
set, the interrupt signal is not generated, although setting the corresponding IRR bit is still
performed.
Bit[15:0]: IMRn
0
1
Description
Corresponding IRR is not masked (IRQ is generated for interrupt conditions)
Corresponding interrupt of IRR is masked (Initial value)
Rev. 2.00 Sep. 07, 2007 Page 839 of 1164
REJ09B0321-0200