SH7201 Datasheet, PDF (269/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 9 Bus State Controller (BSC)
CKIO
A27 to A0
CSn
RD
WR
D31 to D0
Ts Tw1
Twn Tend Tn1 Tn2
(Trd)
Twn Tend Tn1 Tn2
(Trd)
Tnm
Bus access
(first time)
Read cycle wait
A0
Bus access (second
and subsequent times)
Page read cycle wait
A1
CS assert wait
CS delay cycle during
read (end only)
Start enable point
of next bus access
CS delay
cycle during read
RD assert wait
RD assert wait*
Note: * RD assert wait operation during the second and subsequent bus accesses differs depending on the page read
access mode setting value.
Figure 9.4 Basic Bus Timing (Page Read Operation)
Rev. 2.00 Sep. 07, 2007 Page 241 of 1164
REJ09B0321-0200