SH7201 Datasheet, PDF (315/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus Monitor
Section 10 Bus Monitor
The bus monitor is a module that monitors bus errors on each bus. When an illegal address access
or a bus timeout is detected, a bus error interrupt is generated and an access canceling signal is
output for the bus timeout. (The bus timeout function is used for debugging.)
Figure 10.1 shows a block diagram of the bus monitor.
Bus monitor
Peripheral
bus
Bus monitor enable register
Bus monitor status register 1
Bus monitor status register 2
Bus error control register
Bus error signal
SH2A
CPU core
Figure 10.1 Block Diagram of Bus Monitor
10.1 Register Descriptions
The bus monitor has the following registers.
All registers are initialized by a power-on reset or in deep standby mode.
Table 10.1 Register Configuration
Register Name
Bus monitor enable register
Bus monitor status register 1
Bus monitor status register 2
Bus error control register
Abbreviation R/W
SYCBEEN R/W
SYCBESTS1 R/W
SYCBESTS2 R/W
SYCBESW R/W
Initial Value Address
Access
Size
H'00
H'FF400000 8, 16, 32
H'00
H'FF400004 8, 16, 32
H'00
H'FF400008 8, 16, 32
H'00
H'FF40000C 8, 16, 32
Rev. 2.00 Sep. 07, 2007 Page 287 of 1164
REJ09B0321-0200