SH7201 Datasheet, PDF (639/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 13 8-Bit Timers (TMR)
13.5 Operation Timing
13.5.1 TCNT Count Timing
Figure 13.4 shows the TCNT count timing for internal clock input. Figure 13.5 shows the TCNT
count timing for external clock input. Note that the external clock pulse width must be at least 1.5
states for incrementation at a single edge, and at least 2.5 states for incrementation at both edges.
The counter will not increment correctly if the pulse width is less than these values.
Pφ
Internal clock
TCNT input
clock
TCNT
N–1
N
N+1
Figure 13.4 Count Timing for Internal Clock Input at Falling Edge
Pφ
External clock
input pin
TCNT input
clock
TCNT
N–1
N
N+1
Figure 13.5 Count Timing for External Clock Input at Falling and Rising Edges
Rev. 2.00 Sep. 07, 2007 Page 611 of 1164
REJ09B0321-0200