SH7201 Datasheet, PDF (18/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

12.7.15 Reset Sync PWM Mode Buffer Operation and Compare Match Flag .................. 559
12.7.16 Overflow Flags in Reset Synchronous PWM Mode ............................................. 560
12.7.17 Contention between Overflow/Underflow and Counter Clearing......................... 561
12.7.18 Contention between TCNT Write and Overflow/Underflow................................ 562
12.7.19 Cautions on Transition from Normal Operation or
PWM Mode 1 to Reset-Synchronized PWM Mode.............................................. 562
12.7.20 Output Level in Complementary PWM Mode and
Reset-Synchronized PWM Mode ......................................................................... 563
12.7.21 Interrupts in Module Standby Mode ..................................................................... 563
12.7.22 Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection............ 563
12.8 MTU2 Output Pin Initialization......................................................................................... 564
12.8.1 Operating Modes .................................................................................................. 564
12.8.2 Reset Start Operation ............................................................................................ 564
12.8.3 Operation in Case of Re-Setting Due to Error During Operation, etc. ................. 565
12.8.4 Overview of Initialization Procedures and Mode Transitions in
Case of Error during Operation, etc...................................................................... 566
Section 13 8-Bit Timers (TMR) ........................................................................ 597
13.1 Features.............................................................................................................................. 597
13.2 Input/Output Pins............................................................................................................... 599
13.3 Register Descriptions......................................................................................................... 599
13.3.1 Timer Counter (TCNT)......................................................................................... 600
13.3.2 Time Constant Register A (TCORA) ................................................................... 600
13.3.3 Time Constant Register B (TCORB).................................................................... 601
13.3.4 Timer Control Register (TCR).............................................................................. 601
13.3.5 Timer Counter Control Register (TCCR) ............................................................. 603
13.3.6 Timer Control/Status Register (TCSR)................................................................. 605
13.4 Operation ........................................................................................................................... 609
13.4.1 Pulse Output ......................................................................................................... 609
13.4.2 Reset Input............................................................................................................ 610
13.5 Operation Timing............................................................................................................... 611
13.5.1 TCNT Count Timing ............................................................................................ 611
13.5.2 Timing of CMFA and CMFB Setting at Compare Match .................................... 612
13.5.3 Timing of Timer Output at Compare Match......................................................... 612
13.5.4 Timing of Counter Clear by Compare Match ....................................................... 613
13.5.5 Timing of TCNT External Reset........................................................................... 613
13.5.6 Timing of Overflow Flag (OVF) Setting .............................................................. 614
13.6 Operation with Cascaded Connection................................................................................ 614
13.6.1 16-Bit Counter Mode ............................................................................................ 614
13.6.2 Compare Match Count Mode ............................................................................... 615
Rev. 2.00 Sep. 07, 2007 Page xviii of xxviii