SH7201 Datasheet, PDF (148/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 6 Interrupt Controller (INTC)
Register Name
Interrupt priority
register 13
Interrupt priority
register 14
Interrupt priority
register 15
Interrupt priority
register 16
Bits 15 to 12
SCIF6
DMAC5
Reserved
SSI0
Bits 11 to 8
SCIF7
DMAC6
RCAN-ET0
SSI1
Bits 7 to 4
DMINTA
DMAC7
RCAN-ET1
TMR0
Bits 3 to 0
DMAC4
Reserved
Reserved
TMR1
As shown in table 6.3, by setting the 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3
to 0) with values from H'0 (0000) to H'F (1111), the priority of each corresponding interrupt is set.
Setting of H'0 means priority level 0 (the lowest level) and H'F means priority level 15 (the
highest level).
IPR01, IPR02, and IPR05 to IPR16 are initialized to H'0000 by a power-on reset or in deep
standby mode.
Rev. 2.00 Sep. 07, 2007 Page 120 of 1164
REJ09B0321-0200