SH7201 Datasheet, PDF (796/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 18 Serial Sound Interface (SSI)
Figure 18.2 shows a block diagram of the SSI module when it is used alone.
Serial audio bus
SSIDATA
SSI module
Control
circuit
Peripheral bus
Interrupt
request
Register
SSICR
SSISR
SSITDR
SSIRDR
DMA request
Data buffer
Barrel shifter
MSB
Shift register
LSB
SSIWS
Bit counter
SSISCK
Serial clock control
Divider
AUDIO_CLK
AUDIO_X1
AUDIO_X2
[Legend]
SSICR: Control register
SSISR: Status register
SSITDR: Transmit data register
SSIRDR: Receive data register
Figure 18.2 Block Diagram of SSI
Rev. 2.00 Sep. 07, 2007 Page 768 of 1164
REJ09B0321-0200