HD64F7051SFJ20V Datasheet, PDF (88/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 5 Exception Processing
5.3 Address Errors
5.3.1 Address Error Sources
Address errors occur when instructions are fetched or data read or written, as shown in table 5.5.
Table 5.5 Bus Cycles and Address Errors
Bus Cycle
Type
Bus
Master Bus Cycle Description
Instruction CPU
fetch
Instruction fetched from even address
Instruction fetched from odd address
Instruction fetched from other than on-chip
peripheral module space^*
Instruction fetched from on-chip peripheral
module space^*
Instruction fetched from external memory space
when in single chip mode
Data
CPU or
read/write DMAC
Word data accessed from even address
Word data accessed from odd address
Longword data accessed from a longword
boundary
Longword data accessed from other than a
long-word boundary
Byte or word data accessed in on-chip
peripheral module space^*
Longword data accessed in 16-bit on-chip
peripheral module space^*
Longword data accessed in 8-bit on-chip
peripheral module space^*
External memory space accessed when in
single chip mode
Note: * See section 8, Bus State Controller.
Address Errors
None (normal)
Address error occurs
None (normal)
Address error occurs
Address error occurs
None (normal)
Address error occurs
None (normal)
Address error occurs
None (normal)
None (normal)
Address error occurs
Address error occurs
Rev. 5.00 Jan 06, 2006 page 66 of 818
REJ09B0273-0500