HD64F7051SFJ20V Datasheet, PDF (731/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Appendix A On-Chip Supporting Module Registers
Free-Running Counters 1 to 5
H'FFFF82D0 (Channel 1)
16
(TCNT1 to TCNT5)
H'FFFF82CA (Channel 2)
16
H'FFFF820E (Channel 3)
16
H'FFFF8218 (Channel 4)
16
H'FFFF8222 (Channel 5)
16
ATU
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name:
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
15–0
Bit Name
(16-bit up-counter, initial value H'0000)
Description
Counts input clock pulses
General Registers
H'FFFF8210 (Channel 3, 3A) 16
3A to 3D, 4A to 4D, 5A, 5B
H'FFFF8212 (Channel 3, 3B) 16
(GR3A to GR3D, GR4A to GR4D, H'FFFF8214 (Channel 3, 3C) 16
GR5A, GR5B)
H'FFFF8216 (Channel 3, 3D) 16
H'FFFF821A (Channel 4, 4A) 16
H'FFFF821C (Channel 4, 4B) 16
H'FFFF821E (Channel 4, 4C) 16
H'FFFF8220 (Channel 4, 4D) 16
H'FFFF8224 (Channel 5, 5A) 16
H'FFFF8226 (Channel 5, 5B) 16
ATU
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name:
Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
15–0
Bit Name
(Dual-function input capture/output
compare register)
Description
1. Input capture register: Stores TCNT1 value
when input capture signal is generated
2. Output compare register: Set with compare
match value
Rev. 5.00 Jan 06, 2006 page 709 of 818
REJ09B0273-0500