HD64F7051SFJ20V Datasheet, PDF (224/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 10 Advanced Timer Unit (ATU)
Block Diagram of Channel 1: Figure 10.3 shows a block diagram of ATU channel 1.
TSTR
TCLKA
TCLKB
φ/(m·2ⁿ)
1 ≤ m ≤ 32
0≤n≤5
Clock selection
Comparator
Control logic
OVI1
IMIA
IMIB
IMIC
IMID
IMIE
IMIF
TIOA1
TIOB1
TIOC1
TIOD1
TIOE1
TIOF1
TRG0A
TRG1A
OFF1A–1F
Module data bus
Legend:
TSTR: Timer start register (16 bits)
TCR1: Timer control register 1 (8 bits)
TIOR1: Timer I/O control register 1 (8 bits)
TSRB: Timer status register B (8 bits)
TIERB: Timer interrupt enable register B (8 bits)
TCNT1: Free-running counter 1 (16 bits)
GR1: General register 1 (16 bits)
OSBR: Offset base register (16 bits)
Interrupts:
OVI1: Overflow interrupt 1
IMI1: Input capture/compare-match interrupt 1
Inter-channel connection signals:
OFF1: Offset compare-match signal
TRG0A: Channel 0/ICR0A input signal
TRG1A: Channel 1/GR1A compare-match signal
Figure 10.3 Block Diagram of Channel 1
Rev. 5.00 Jan 06, 2006 page 202 of 818
REJ09B0273-0500