HD64F7051SFJ20V Datasheet, PDF (132/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 8 Bus State Controller (BSC)
8.1.2 Block Diagram
Figure 8.1 shows the BSC block diagram.
On-chip
memory
control unit
WAIT
Wait
control unit
CS0–CS3
Area
control unit
RAMER
Bus interface
WCR1
WCR2
BCR1
BCR2
RD
WRH, WRL
Memory
control unit
BSC
WCR1: Wait control register 1
WCR2: Wait control register 2
RAMER: RAM emulation register
BCR1: Bus control register 1
BCR2: Bus control register 2
Figure 8.1 BSC Block Diagram
Rev. 5.00 Jan 06, 2006 page 110 of 818
REJ09B0273-0500