HD64F7051SFJ20V Datasheet, PDF (624/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 19 ROM (256 kB Version)
19.5.4 Erase Block Register 2 (EBR2)
EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is
initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low
level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE bit in
FLMCR1 is not set. When a bit in EBR2 is set to 1, the corresponding block can be erased. Other
blocks are erase-protected. Only one of the bits of EBR1 and EBR2 combined can be set. Do not
set more than one bit. When on-chip flash memory is disabled, a read will return H'00, and writes
are invalid.
The flash memory block configuration is shown in table 19.3.
Bit: 7
6
5
4
3
2
1
0
EB11 EB10 EB9 EB8 EB7 EB6 EB5 EB4
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Table 19.3 Flash Memory Erase Blocks
Block (Size)
EB0 (32 kB)
EB1 (32 kB)
EB2 (32 kB)
EB3 (32 kB)
EB4 (32 kB)
EB5 (32 kB)
EB6 (32 kB)
EB7 (28 kB)
EB8 (1 kB)
EB9 (1 kB)
EB10 (1 kB)
EB11 (1 kB)
Address
H'000000–H'007FFF
H'008000–H'00FFFF
H'010000–H'017FFF
H'018000–H'01FFFF
H'020000–H'027FFF
H'028000–H'02FFFF
H'030000–H'037FFF
H'038000–H'03EFFF
H'03F000–H'03F3FF
H'03F400–H'03F7FF
H'03F800–H'03FBFF
H'03FC00–H'03FFFF
Rev. 5.00 Jan 06, 2006 page 602 of 818
REJ09B0273-0500