HD64F7051SFJ20V Datasheet, PDF (138/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 8 Bus State Controller (BSC)
Bit 2: A2SZ
0
1
Description
Byte (8 bit) size
Word (16 bit) size (initial value)
Bit 1—CS1 Space Size Specification (A1SZ): Specifies the CS1 space bus size. A 0 setting
specifies byte (8-bit) size, and a 1 setting specifies word (16-bit) size.
Bit 1: A1SZ
0
1
Description
Byte (8 bit) size
Word (16 bit) size (initial value)
Bit 0—CS0 Space Size Specification (A0SZ): Specifies the CS0 space bus size A 0 setting
specifies byte (8-bit) size, and a 1 setting specifies word (16-bit) size.
Bit 0: A0SZ
Description
0
Byte (8 bit) size
1
Word (16 bit) size (initial value)
Note: A0SZ is effective only in on-chip ROM effective mode. In on-chip ROM ineffective mode,
the CS0 space bus size is specified by the mode pin.
8.2.2 Bus Control Register 2 (BCR2)
Bit:
Initial value:
R/W:
15
IW31
1
R/W
14
IW30
1
R/W
13
IW21
1
R/W
12
IW20
1
R/W
11
IW11
1
R/W
10
IW10
1
R/W
9
IW01
1
R/W
8
IW00
1
R/W
Bit:
Initial value:
R/W:
7
CW3
1
R/W
6
CW2
1
R/W
5
CW1
1
R/W
4
CW0
1
R/W
3
SW3
1
R/W
2
SW2
1
R/W
1
SW1
1
R/W
0
SW0
1
R/W
BCR2 is a 16-bit read/write register that specifies the number of idle cycles and CS signal assert
extension of each CS space.
BCR2 is initialized by a power-on reset and in hardware standby mode to H'FFFF. It is not
initialized by software standby mode.
Rev. 5.00 Jan 06, 2006 page 116 of 818
REJ09B0273-0500