HD64F7051SFJ20V Datasheet, PDF (692/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 22 Electrical Characteristics
22.3.7 Watchdog Timer Timing
Table 22.10 Watchdog Timer Timing
Conditions: V_CC = 5.0 V ± 10%, AV_CC = 5.0 V ± 10%, AV_REF = 4.5 V to AV_CC, V_SS = AV_SS = 0 V,
Ta = –40 to +85°C
Item
WDTOVF delay time
Symbol
t
WOVD
Min
—
Max
Unit
Figure
100
ns
22.17
CK
WDTOVF
t_WOVD
t_WOVD
Figure 22.17 Watchdog Timer Timing
22.3.8 Serial Communication Interface Timing
Table 22.11 Serial Communication Interface Timing
Conditions: V_CC = 5.0 V ± 10%, AV_CC = 5.0 V ± 10%, AV_REF = 4.5 V to AV_CC, V_SS = AV_SS = 0 V,
Ta = –40 to +85°C
Item
Input clock cycle
Input clock cycle (clock sync)
Input clock pulse width
Input clock rise time
Input clock fall time
Transmit data delay time (clock sync)
Receive data setup time (clock sync)
Receive data hold time (clock sync)
Symbol
t_scyc
t_scyc
t_sckw
t_sckr
t
sckf
t
TXD
t_RXS
t_RXH
Min
4
6
0.4
—
—
—
100
100
Max
—
—
0.6
1.5
1.5
100
—
—
Unit
t_cyc
t_cyc
t_scyc
t_cyc
t
cyc
ns
ns
ns
Figure
22.18
22.19
Rev. 5.00 Jan 06, 2006 page 670 of 818
REJ09B0273-0500