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HD64F7051SFJ20V Datasheet, PDF (65/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC | |||
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Section 2 CPU
Instruction
DMULS.L Rm,Rn
DMULU.L Rm,Rn
DT
Rn
EXTS.B Rm,Rn
EXTS.W Rm,Rn
EXTU.B Rm,Rn
EXTU.W Rm,Rn
MAC.L @Rm+,@Rn+
MAC.W @Rm+,@Rn+
MUL.L Rm,Rn
MULS.W Rm,Rn
MULU.W Rm,Rn
NEG
NEGC
Rm,Rn
Rm,Rn
Instruction Code
0011nnnnmmmm1101
0011nnnnmmmm0101
0100nnnn00010000
0110nnnnmmmm1110
0110nnnnmmmm1111
0110nnnnmmmm1100
0110nnnnmmmm1101
0000nnnnmmmm1111
0100nnnnmmmm1111
0000nnnnmmmm0111
0010nnnnmmmm1111
0010nnnnmmmm1110
0110nnnnmmmm1011
0110nnnnmmmm1010
Operation
Signed operation of
Rn à Rm â MACH,
MACL 32 Ã 32 â 64 bit
Unsigned operation of
Rn à Rm â MACH,
MACL 32 Ã 32 â 64 bit
Rn â 1 â Rn, when Rn
is 0, 1 â T. When Rn
is nonzero, 0 â T
A byte in Rm is sign-
extended â Rn
A word in Rm is sign-
extended â Rn
A byte in Rm is zero-
extended â Rn
A word in Rm is zero-
extended â Rn
Signed operation of
(Rn) Ã (Rm) + MAC â
MAC 32 Ã 32 + 64 â
64 bit
Signed operation of
(Rn) Ã (Rm) + MAC â
MAC 16 Ã 16 + 64 â
64 bit
Rn à Rm â MACL,
32 Ã 32 â 32 bit
Signed operation of
Rn à Rm â MAC
16 Ã 16 â 32 bit
Unsigned operation of
Rn à Rm â MAC
16 Ã 16 â 32 bit
0âRm â Rn
0âRmâT â Rn, Borrow
âT
Execu-
tion
Cycles
2 to 4*
2 to 4*
1
1
1
1
1
3/
(2 to 4)*
3/(2)*
2 to 4*
1 to 3*
1 to 3*
1
1
T Bit
â
â
Comparison
result
â
â
â
â
â
â
â
â
â
â
Borrow
Rev. 5.00 Jan 06, 2006 page 43 of 818
REJ09B0273-0500
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