HD64F7051SFJ20V Datasheet, PDF (146/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 8 Bus State Controller (BSC)
8.3 Accessing Ordinary Space
A strobe signal is output by ordinary space accesses to provide primarily for SRAM or ROM
direct connections.
8.3.1 Basic Timing
Figure 8.3 shows the basic timing of ordinary space access. Ordinary access bus cycles are
performed in 2 states.
T₁
T₂
CK
Address
CSn
Read
RD
Data
Write
WRx
Data
Figure 8.3 Basic Timing of Ordinary Space Access
Rev. 5.00 Jan 06, 2006 page 124 of 818
REJ09B0273-0500