HD64F7051SFJ20V Datasheet, PDF (547/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 17 I/O Ports (I/O)
17.5.1 Register Configuration
The port D register is shown in table 17.7.
Table 17.7 Port D Register
Name
Abbreviation R/W Initial Value Address
Port D data register
PDDR
R/W H'0000
H'FFFF8398
Note: A register access is performed in two cycles regardless of the access size.
Access Size
8, 16
17.5.2 Port D Data Register (PDDR)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
DR DR DR DR DR DR DR DR DR DR DR DR DR DR DR DR
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The port D data register (PDDR) is a 16-bit readable/writable register that stores port D data. Bits
PD15DR to PD0DR correspond to pins PD15/D15 to PD0/D0.
When a pin functions as a general output, if a value is written to PDDR, that value is output
directly from the pin, and if PDDR is read, the register value is returned directly regardless of the
pin state. When the POD pin is driven low, general outputs go to the high-impedance state
regardless of the PDDR value. When the POD pin is driven high, the written value is output from
the pin.
When a pin functions as a general input, if PDDR is read the pin state, not the register value, is
returned directly. If a value is written to PDDR, although that value is written into PDDR it does
not affect the pin state. Table 17.8 summarizes port D data register read/write operations.
PDDR is initialized by a power-on reset (excluding a WDT power-on reset), and in hardware
standby mode. It is not initialized in software standby mode or sleep mode.
Rev. 5.00 Jan 06, 2006 page 525 of 818
REJ09B0273-0500