HD64F7051SFJ20V Datasheet, PDF (85/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 5 Exception Processing
5.1.3 Exception Processing Vector Table
Before exception processing begins running, the exception processing vector table must be set in
memory. The exception processing vector table stores the start addresses of exception service
routines. (The reset exception processing table holds the initial values of PC and SP.)
All exception sources are given different vector numbers and vector table address offsets, from
which the vector table addresses are calculated. During exception processing, the start addresses of
the exception service routines are fetched from the exception processing vector table, which
indicated by this vector table address.
Table 5.3 shows the vector numbers and vector table address offsets. Table 5.4 shows how vector
table addresses are calculated.
Table 5.3 Exception Processing Vector Table
Exception Sources
Power-on reset
PC
SP
(Reserved by system)
(Reserved by system)
General illegal instruction
(Reserved by system)
Slot illegal instruction
(Reserved by system)
(Reserved by system)
CPU address error
DMAC address error
Interrupts
NMI
User break
(Reserved by system)
Trap instruction (user vector)
Vector
Numbers
0
1
2
3
4
5
6
7
8
9
10
11
12
13
:
31
32
:
63
Vector Table Address Offset
H'00000000–H'00000003
H'00000004–H'00000007
H'00000008–H'0000000B
H'0000000C–H'0000000F
H'00000010–H'00000013
H'00000014–H'00000017
H'00000018–H'0000001B
H'0000001C–H'0000001F
H'00000020–H'00000023
H'00000024–H'00000027
H'00000028–H'0000002B
H'0000002C–H'0000002F
H'00000030–H'00000033
H'00000034–H'00000037
:
H'0000007C–H'0000007F
H'00000080–H'00000083
:
H'000000FC–H'000000FF
Rev. 5.00 Jan 06, 2006 page 63 of 818
REJ09B0273-0500