HD64F7051SFJ20V Datasheet, PDF (330/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 10 Advanced Timer Unit (ATU)
OVF Setting Timing in Overflow: When TCNT overflows (from H'FFFF to H'0000, or from
H'FFFFFFFF to H'00000000), the OVF bit is set to 1 in the timer status register (TSR).
The timing in this case is shown in figure 10.32.
CK
TCNT input clock
TCNT ^H'FFFF
Overflow signal
H'0000
Interrupt status flag
OVF
Interrupt request signal
OVI
Figure 10.32 OVF Setting Timing in Overflow
Rev. 5.00 Jan 06, 2006 page 308 of 818
REJ09B0273-0500