HD64F7051SFJ20V Datasheet, PDF (113/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 6 Interrupt Controller (INTC)
6.4.2 Stack after Interrupt Exception Processing
Figure 6.4 shows the stack after interrupt exception processing.
Address
4n–8
4n–4
4n
PC^*1
SR
32 bits
32 bits
SP^*2
Notes: 1. PC: Start address of the next instruction (return destination instruction)
after the executing instruction
2. Always be certain that SP is a multiple of 4
Figure 6.4 Stack after Interrupt Exception Processing
Rev. 5.00 Jan 06, 2006 page 91 of 818
REJ09B0273-0500