HD64F7051SFJ20V Datasheet, PDF (214/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 9 Direct Memory Access Controller (DMAC)
Table 9.10 DMAC Internal Status
Item
Address Reload On
Address Reload Off
SAR
H'FFFF83F0
H'FFFF83F4
DAR
H'00400004
H'00400004
DMATCR
H'0000007C
H'0000007C
Bus rights
Released
Maintained
DMAC operation
Halted
Processing continues
Interrupts
Not issued
Not issued
Transfer request source flag clear Executed
Not executed
Notes: 1. Interrupts are executed until the DMATCR value becomes 0, and if the IE bit of the
CHCR is set to 1, are issued regardless of whether the address reload is on or off.
2. If transfer request source flag clears are executed until the DMATCR value becomes 0,
they are executed regardless of whether the address reload is on or off.
3. Designate burst mode when using the address reload function. There are cases where
abnormal operation will result if it is executed in cycle steal mode.
4. Designate a multiple of four for the TCR value when using the address reload function.
There are cases where abnormal operation will result if anything else is designated.
To execute transfers after the fifth one when the address reload is on, make the transfer request
source issue another transfer request signal.
9.4.4
Example of DMA Transfer between External Memory and SCI1 Send Side
(Indirect Address On)
In this example, DMAC channel 3 is used, an indirect address designated external memory is the
transfer source and the SCI1 sending side is the transfer destination.
Table 9.11 indicates the transfer conditions and the setting values of each of the registers.
Rev. 5.00 Jan 06, 2006 page 192 of 818
REJ09B0273-0500