HD64F7051SFJ20V Datasheet, PDF (403/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 13 Serial Communication Interface (SCI)
Bit 7—Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data
from the TDR into the TSR and new serial transmit data can be written in the TDR.
Bit 7: TDRE
0
1
Description
TDR contains valid transmit data
TDRE is cleared to 0 when software reads TDRE after it has been set to 1, then
writes 0 in TDRE or the DMAC writes data in TDR
TDR does not contain valid transmit data (initial value)
TDRE is set to 1 when the chip is power-on reset or enters standby mode, the
TE bit in the serial control register (SCR) is cleared to 0, or TDR contents are
loaded into TSR, so new data can be written in TDR
Bit 6—Receive Data Register Full (RDRF): Indicates that RDR contains received data.
Bit 6: RDRF Description
0
RDR does not contain valid received data (initial value)
RDRF is cleared to 0 when the chip is power-on reset or enters standby mode,
software reads RDRF after it has been set to 1, then writes 0 in RDRF, or the
DMAC reads data from RDR
1
RDR contains valid received data
RDRF is set to 1 when serial data is received normally and transferred from RSR
to RDR
Note:
The RDR and RDRF are not affected by detection of receive errors or by clearing of the RE
bit to 0 in the serial control register. They retain their previous contents. If RDRF is still set
to 1 when reception of the next data ends, an overrun error (ORER) occurs and the
received data is lost.
Rev. 5.00 Jan 06, 2006 page 381 of 818
REJ09B0273-0500