HD64F7051SFJ20V Datasheet, PDF (753/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Appendix A On-Chip Supporting Module Registers
Offset Base Register (OSBR)
H'FFFF82DE (Channel 1) 16
ATU
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name:
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R R R R R R R R R R R R
Bit
15–0
Bit Name
Dedicated input capture register with
signal from channel 0 ICR0A as input
trigger
Description
Stores TCNT1 value at edge(s) selected by
TIORA bits 0 and 1
Rev. 5.00 Jan 06, 2006 page 731 of 818
REJ09B0273-0500