HD64F7051SFJ20V Datasheet, PDF (830/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Appendix A On-Chip Supporting Module Registers
A.3 Register States at Reset and in Power-Down State
Type
CPU
Interrupt controller
(INTC)
User break controller
(UBC)
Bus state controller
(BSC)
Direct memory
access controller
(DMAC)
Reset
Registers
(Abbreviations)
Power-
On
R0–R15
Initialized
SR
GBR
VBR
MACH, MACL
PR
PC
IPRA–IPRH
Initialized
ICR
ISR
UBARH, UBARL
Initialized
UBAMRH, UBAMRL
UBBR
BCR1, BCR2
Initialized
WCR1, WCR2
SAR0–SAR3
Initialized
DAR0–DAR3
DMATCR0–DMATCR3
CHCR0–CHCR3
DMAOR
Power-Down State
Hardware Software
Standby Standby Sleep
Initialized Held
Held
Initialized Held
Held
Initialized Held
Held
Initialized Held
Held
Initialized Initialized Held
Rev. 5.00 Jan 06, 2006 page 808 of 818
REJ09B0273-0500