HD64F7051SFJ20V Datasheet, PDF (125/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 7 User Break Controller (UBC)
UBARH/UBARL
UBAMRH/UBAMRL
Internal address
bits 31–0
32
32
CP1 CP0
32
32
32
CPU cycle
DMA cycle
ID1 ID0
Instruction fetch
Data access
RW1 RW0
Read cycle
User
break
interrupt
Write cycle
SZ1 SZ0
Byte size
Word size
Longword size
Figure 7.2 Break Condition Judgment Method
Rev. 5.00 Jan 06, 2006 page 103 of 818
REJ09B0273-0500