HD64F7051SFJ20V Datasheet, PDF (177/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 9 Direct Memory Access Controller (DMAC)
In order to output a transfer request from an on-chip peripheral module, set the relevant interrupt
enable bit for each module, and output an interrupt signal.
When an on-chip peripheral module’s interrupt request signal is used as a DMA transfer request
signal, interrupts for the CPU are not generated.
When a DMA transfer is conducted corresponding with one of the transfer request signals in table
9.4, it is automatically discontinued. In cycle steal mode this occurs in the first transfer, and in
burst mode with the last transfer.
9.3.3 Channel Priority
When the DMAC receives simultaneous transfer requests on two or more channels, it selects a
channel according to a predetermined priority order, either in a fixed mode or in round robin
mode. These modes are selected by priority bits PR1 and PR0 in the DMA operation register
(DMAOR).
Fixed Mode: In these modes, the priority levels among the channels remain fixed.
The following priority orders are available for fixed mode:
• CH0 > CH1 > CH2 > CH3
• CH0 > CH2 > CH3 > CH1
• CH2 > CH0 > CH1 > CH3
These are selected by settings of the PR1 and PR0 bits of the DMA operation register (DMAOR).
Round Robin Mode: In round robin mode, each time the transfer of one transfer unit (byte, word
or long word) ends on a given channel, that channel receives the lowest priority level (figure 9.3).
The priority level in round robin mode immediately after a reset is CH0 > CH1 > CH2 > CH3.
Rev. 5.00 Jan 06, 2006 page 155 of 818
REJ09B0273-0500