HD64F7051SFJ20V Datasheet, PDF (25/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 1 Overview
Item
Operating states
Interrupt
controller (INTC)
User break
controller (UBC)
Clock pulse
generator
(CPG/PLL)
Features
• Operating modes
 Single-chip mode
 8/16-bit bus expanded mode (area 0 only set by mode pins)
• Mode with on-chip ROM
• Mode with no on-chip ROM
• Processing states
 Power-on reset state
 Program execution state
 Exception handling state
 Bus-released state
 Power-down state
• Power-down state
 Sleep mode
 Software standby mode
 Hardware standby mode
• Nine external interrupt pins (NMI, IRQ0 to IRQ7)
• 66 internal interrupt sources
(ATU × 44, SCI × 12, DMAC × 4, A/D × 2, WDT × 1, UBC × 1, CMT × 2)
• 16 programmable priority levels
• Requests an interrupt when the CPU or DMAC generates a bus cycle with
specified conditions
• Simplifies configuration of an on-chip debugger
• On-chip clock pulse generator (maximum operating frequency: 20 MHz)
• On-chip clock-multiplication PLL circuit (×1, ×2, ×4)
External input frequency range: 4 to 10 MHz
Rev. 5.00 Jan 06, 2006 page 3 of 818
REJ09B0273-0500