HD64F7051SFJ20V Datasheet, PDF (685/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 22 Electrical Characteristics
T1
T2
CK
A21–A0
CSn
RD
(During read)
D15–D0
(During read)
WRx
(During write)
D15–D0
(During write)
DACKn
t_AD
t_CSD1
t_CSD2
t_RSD1
t_OE
t_ACC
t_RSD2
t_RDS
t_RDH
t_WSD1
t_AS
t_WDD
t_DACKD
t_WSD2
t_WR
t_WDH
t_DACKD
Note: t_RDH is specified from the first negate timing for A21–A0, CSn, and RD.
Figure 22.8 Basic Cycle (No Waits)
Rev. 5.00 Jan 06, 2006 page 663 of 818
REJ09B0273-0500