HD64F7051SFJ20V Datasheet, PDF (249/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 10 Advanced Timer Unit (ATU)
Bits 3 and 2—I/O Control 0B1 and 0B0 (IO0B1, IO0B0): These bits select input capture
register 0B (ICR0B) edge detection.
Bit 3:
IO0B1
0
1
Bit 2:
IO0B0
0
1
0
1
Description
Input capture disabled
Input capture in ICR0B on rising edge
Input capture in ICR0B on falling edge
Input capture in ICR0B on both rising and falling edges
(Initial value)
Bits 1 and 0—I/O Control 0A1 and 0A0 (IO0A1, IO0A0): These bits select input capture
register 0A (ICR0A) and offset base register (OSBR) edge detection.
Bit 1:
IO0A1
0
1
Bit 0:
IO0A0
0
1
0
1
Description
Input capture disabled
Input capture in ICR0A on rising edge
Input capture in ICR0A on falling edge
Input capture in ICR0A on both rising and falling edges
(Initial value)
Rev. 5.00 Jan 06, 2006 page 227 of 818
REJ09B0273-0500