HD64F7051SFJ20V Datasheet, PDF (313/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 10 Advanced Timer Unit (ATU)
from the CPU before the next match with the general register, one-shot pulses can be output
consecutively. DSTR cannot be rewritten while the offset one-shot pulse function is being used.
By making the appropriate setting in timer interrupt enable register F (TIERF), an interrupt request
can be sent to the CPU one clock cycle after the corresponding down-counter (DCNT10A to
DCNT10H) reaches 0.
It is possible to forcibly output 0 to the output pin during the down-count by clearing DCNT to 0
(since DST cannot be cleared to 0 by the user program). In this case, DCNT and the relevant DST
bit are automatically cleared to 0 when the DCNT value underflows, and DCNT stops counting.
At the same time, 0 is output to the corresponding external pin.
An example of offset one-shot pulse operation is shown in figure 10.16.
In the example in figure 10.16, the ATU channel 1 free-running counter is started, and offset one-
shot pulse output is performed by means of GR1A output compare-match and the DCNT10A
channel 10 down-counter corresponding to GR1A.
H'FFFF
GR1A
Counter value
TCNT1
H'0000
Write to GR1A
Write to DCNT10A
by user program
(dataA)
(dataB)
Time
H'FFFF
data B
data A
H'0000
TOA10
Offset
One-
shot
pulse
Down-count value
DCNT10A
Offset
One-shot
pulse
Figure 10.16 Example of Offset One-Shot Pulse Operation
Rev. 5.00 Jan 06, 2006 page 291 of 818
REJ09B0273-0500