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HD64F7051SFJ20V Datasheet, PDF (834/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC | |||
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Appendix B Pin States
Appendix B Pin States
B.1 Pin States at Reset and in Power-Down, and Bus Right Released
State
Table B.1 shows the SH7050 pin states at reset and in power-down, and bus right released state.
Table B.1 Pin States at Reset and in Power-Down, and Bus Right Released State
Pin Function
Pin State
Reset
Power-Down
Item
Pins
Power-On Reset by RES pin
Bus-
ROMless,
Expanded,
8-Bit
ROMless,
Expanded,
16-Bit
Expanded,
with ROM
Single-
Chip
Hardware
Standby
Software
Standby
Released
Sleep State
Clock
EXTAL
I
I
I
I
Z
Z
I
I
XTAL
CK
O
O
O
O
Z
Z
O
O
O
O
O
O
Z
H*
O
O
Operating FWE,
I
I
I
I
I
I
I
I
Mode
MD0âMD3
Selection HSTBY
I
I
I
I
I
I
I
I
System RES
I
I
I
I
I
I
I
I
Control WDTOVF
O
O
O
O
Z
H*
O
O
BREQ
â
â
â
â
Z
Z
I
I
BACK
â
â
â
â
Z
Z
O
O
Interrupt NMI
I
I
I
I
I
I
I
I
IRQ0â
IRQ7
â
â
â
â
Z
Z
I
I
IRQOUT
â
â
â
â
Z
H*
O
O
Address A0âA21
L
Bus
L
â
â
Z
Z
O
Z
Data Bus D0âD7
Z
Z
â
â
Z
Z
I/O
Z
D8âD15
â
Z
â
â
Z
Z
I/O
Z
Rev. 5.00 Jan 06, 2006 page 812 of 818
REJ09B0273-0500
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