HD64F7051SFJ20V Datasheet, PDF (332/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 10 Advanced Timer Unit (ATU)
Timing of IIF Setting by Interval Timer: When 1 is generated by ANDing the rise of bit 10–13
in free-running counter TCNT0L with bit ITVE0–ITVE3 in the interval interrupt request register
(ITVRR), the IIF bit is set to 1 in the timer status register (TSR).
The timing in this case is shown in figure 10.34. TCNT0 value N in the figure is the counter value
when TCNT0L bit 10–13 changes to 1. (For example, N = H'00000400 in the case of bit 10,
H'00000800 in the case of bit 11, etc.)
CK
TCNT input clock
TCNT0
N–1
N
Internal interval signal
Interrupt status flag
IIF
Interrupt request signal
Figure 10.34 Timing of IIF Setting Timing by Interval Timer
Rev. 5.00 Jan 06, 2006 page 310 of 818
REJ09B0273-0500