HD64F7051SFJ20V Datasheet, PDF (54/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 2 CPU
Addressing
Mode
PC relative
addressing
Instruction
Format Effective Addresses Calculation
disp:8
The effective address is the PC value sign-extended
with an 8-bit displacement (disp), doubled, and
added to the PC value.
Equation
PC + disp × 2
PC
disp
+
(sign-extended)
×
PC + disp × 2
2
disp:12 The effective address is the PC value sign-extended PC + disp × 2
with a 12-bit displacement (disp), doubled, and
added to the PC value.
PC
disp
+
(sign-extended)
×
PC + disp × 2
2
Rn
The effective address is the register PC value
PC + Rn
plus Rn.
PC
+
PC + Rn
Immediate
addressing
Rn
#imm:8 The 8-bit immediate data (imm) for the TST, AND, —
OR, and XOR instructions are zero-extended.
#imm:8 The 8-bit immediate data (imm) for the MOV, ADD, —
and CMP/EQ instructions are sign-extended.
#imm:8 The 8-bit immediate data (imm) for the TRAPA
—
instruction is zero-extended and is quadrupled.
Rev. 5.00 Jan 06, 2006 page 32 of 818
REJ09B0273-0500