HD64F7051SFJ20V Datasheet, PDF (670/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 21 Power-Down State
Table 21.4 Register States in the Standby Mode
Module
Interrupt controller (INTC)
User break controller (UBC)
Bus state controller (BSC)
Direct memory access
controller (DMAC)
Advanced timer unit (ATU)
Advanced pulse controller
Watchdog timer
(WDT)
Compare match timer (CMT)
Serial communication
interface (SCI)
A/D converter (A/D)
Pin function controller (PFC)
I/O port (I/O)
Power-down state related
Registers Initialized
—
—
—
All registers
All registers
—
• Bits 7–5 (OVF, WT/IT, TME)
of the timer control status
register (TCSR)
• Reset control/status register
(RSTCSR)
• Timer counter (TCNT)
All registers
All registers
All registers
—
—
—
Registers that Retain Data
All registers
All registers
All registers
—
—
All registers
• Bits 2–0 (CKS2–CKS0) of
the TCSR
—
—
—
All registers
All registers
• Standby control register
(SBYCR)
• System control register
(SYSCR)
Rev. 5.00 Jan 06, 2006 page 648 of 818
REJ09B0273-0500