HD64F7051SFJ20V Datasheet, PDF (171/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 9 Direct Memory Access Controller (DMAC)
Bits 9–8—Priority Mode 1 and 0 (PR1 and PR0): These bits determine the priority level of
channels for execution when transfer requests are made for several channels simultaneously.
Bit 9: PR1
0
0
1
1
Bit 8: PR0
0
1
0
1
Description
CH0 > CH1 > CH2 > CH3 (initial value)
CH0 > CH2 > CH3 > CH1
CH2 > CH0 > CH1 > CH3
Round robin mode
Bit 2—Address Error Flag (AE): Indicates that an address error has occurred during DMA
transfer. If this bit is set during a data transfer, transfers on all channels are suspended. The CPU
cannot write a 1 to the AE bit. Clearing is effected by 0 write after 1 read.
Bit 2: AE
0
1
Description
No address error, DMA transfer enabled (initial value)
Clearing condition: Write AE = 0 after reading AE = 1
Address error, DMA transfer disabled
Setting condition: Address error due to DMAC
Bit 1—NMI Flag (NMIF): Indicates input of an NMI. This bit is set irrespective of whether the
DMAC is operating or suspended. If this bit is set during a data transfer, transfers on all channels
are suspended. The CPU is unable to write a 1 to the NMIF. Clearing is effected by 0 write after 1
read.
Bit 1: NMIF
0
1
Description
No NMI interrupt, DMA transfer enabled (initial value)
Clearing condition: Write NMIF = 0 after reading NMIF = 1
NMI has occurred, DMC transfer prohibited
Set condition: NMI interrupt occurrence
Bit 0—DMAC Master Enable (DME): This bit enables activation of the entire DMAC. When
the DME bit and DE bit of the CHCR for the corresponding channel are set to 1, that channel is
transfer-enabled. If this bit is cleared during a data transfer, transfers on all channels are
suspended.
Rev. 5.00 Jan 06, 2006 page 149 of 818
REJ09B0273-0500