HD64F7051SFJ20V Datasheet, PDF (492/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 15 Compare Match Timer (CMT)
15.5.2 Contention between CMCNT Word Write and Incrementation
If an increment occurs during the T₂ state of the CMCNT counter word write cycle, the counter
write has priority, so no increment occurs. Figure 15.7 shows the timing.
CMCNT write cycle
T₁
T₂
CK
Address
CMCNT
Internal
write signal
Compare
match signal
CMCNT
N
M
CMCNT write data
Figure 15.7 CMCNT Word Write and Increment Contention
Rev. 5.00 Jan 06, 2006 page 470 of 818
REJ09B0273-0500