HD64F7051SFJ20V Datasheet, PDF (248/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 10 Advanced Timer Unit (ATU)
For general registers (GR), TIOR selects use as an input capture register or output compare
register, and performs edge detection setting. For channels 3 to 5, TIOR also selects enabling or
disabling of free-running counter (TCNT) clearing.
Each TIOR is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
Timer I/O Control Register 0A (TIOR0A)
Timer I/O control register 0A (TIOR0A) is an 8-bit register. Channel 1 has one TIOR register.
Bit:
Initial value:
R/W:
7
IO0D1
0
R/W
6
IO0D0
0
R/W
5
IO0C1
0
R/W
4
IO0C0
0
R/W
3
IO0B1
0
R/W
2
IO0B0
0
R/W
1
IO0A1
0
R/W
0
IO0A0
0
R/W
TIOR0A specifies edge detection for input capture registers ICR0A to ICR0D.
Bits 7 and 6—I/O Control 0D1 and 0D0 (IO0D1, IO0D0): These bits select input capture
register 0D (ICR0D) edge detection.
Bit 7:
IO0D1
0
1
Bit 6:
IO0D0
0
1
0
1
Description
Input capture disabled
Input capture in ICR0D on rising edge
Input capture in ICR0D on falling edge
Input capture in ICR0D on both rising and falling edges
(Initial value)
Bits 5 and 4—I/O Control 0C1 and 0C0 (IO0C1, IO0C0): These bits select input capture
register 0C (ICR0C) edge detection.
Bit 5:
IO0C1
0
1
Bit 4:
IO0C0
0
1
0
1
Description
Input capture disabled
Input capture in ICR0C on rising edge
Input capture in ICR0C on falling edge
Input capture in ICR0C on both rising and falling edges
(Initial value)
Rev. 5.00 Jan 06, 2006 page 226 of 818
REJ09B0273-0500