|
HD64F7051SFJ20V Datasheet, PDF (63/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC | |||
|
◁ |
Section 2 CPU
Instruction
Instruction Code Operation
Execu-
tion
Cycles T Bit
MOV.W Rm,@(R0,Rn)
0000nnnnmmmm0101 Rm â (R0 + Rn)
1
â
MOV.L Rm,@(R0,Rn)
0000nnnnmmmm0110 Rm â (R0 + Rn)
1
â
MOV.B @(R0,Rm),Rn
0000nnnnmmmm1100 (R0 + Rm) â Sign
extension â Rn
1
â
MOV.W @(R0,Rm),Rn
0000nnnnmmmm1101 (R0 + Rm) â Sign
extension â Rn
1
â
MOV.L @(R0,Rm),Rn
0000nnnnmmmm1110 (R0 + Rm) â Rn
1
â
MOV.B R0,@(disp,GBR) 11000000dddddddd R0 â (disp + GBR)
1
â
MOV.W R0,@(disp,GBR) 11000001dddddddd R0 â (disp à 2 + GBR)
1
â
MOV.L R0,@(disp,GBR) 11000010dddddddd R0 â (disp à 4 + GBR)
1
â
MOV.B @(disp,GBR),R0 11000100dddddddd (disp + GBR) â Sign
extension â R0
1
â
MOV.W @(disp,GBR),R0 11000101dddddddd (disp à 2 + GBR) â Sign 1
â
extension â R0
MOV.L @(disp,GBR),R0 11000110dddddddd (disp à 4 + GBR) â R0
1
â
MOVA @(disp,PC),R0 11000111dddddddd disp à 4 + PC â R0
1
â
MOVT Rn
0000nnnn00101001 T â Rn
1
â
SWAP.B Rm,Rn
0110nnnnmmmm1000 Rm â Swap the bottom two 1
â
bytes â Rn
SWAP.W Rm,Rn
0110nnnnmmmm1001 Rm â Swap two
1
â
consecutive words â Rn
XTRCT Rm,Rn
0010nnnnmmmm1101 Rm: Middle 32 bits of
Rn â Rn
1
â
Rev. 5.00 Jan 06, 2006 page 41 of 818
REJ09B0273-0500
|
▷ |