HD64F7051SFJ20V Datasheet, PDF (328/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 10 Advanced Timer Unit (ATU)
10.4 Interrupts
The ATU has 44 interrupt sources of five kinds: input capture interrupts, compare-match
interrupts, overflow interrupts, underflow interrupts, and interval interrupts.
10.4.1 Status Flag Setting Timing
IMF (ICF) Setting Timing in Input Capture: When an input capture signal is generated, the
IMF bit (ICF bit in case of channel 0) is set to 1 in the timer status register (TSR), and the TCNT
value is simultaneously transferred to the corresponding GR (ICR in the case of channel 0).
The timing in this case is shown in figure 10.30.
In the example in figure 10.30, a signal is input from an external pin, and input capture is
performed on detection of a rising edge.
CK
Input capture input
Internal input capture
signal
TCNT
t_TICS (input capture input setup time)
N
GR (ICR)
N
Interrupt status flag
IMF (ICF)
Interrupt request signal
IMI (ICI)
Figure 10.30 IMF (ICF) Setting Timing in Input Capture
Rev. 5.00 Jan 06, 2006 page 306 of 818
REJ09B0273-0500