HD64F7051SFJ20V Datasheet, PDF (60/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 2 CPU
Operation
Classification Types Code
Function
System
control
11
CLRMAC MAC register clear
CLRT
T bit clear
LDC
Load to control register
LDS
Load to system register
NOP
No operation
RTE
Return from exception processing
SETT
T bit set
SLEEP Shift into power-down mode
STC
Storing control register data
STS
Storing system register data
TRAPA Trap exception handling
Total: 62
No. of
Instructions
31
142
Table 2.11 shows the format used in tables 2.12 to 2.17, which list instruction codes, operation,
and execution states in order by classification.
Rev. 5.00 Jan 06, 2006 page 38 of 818
REJ09B0273-0500