HD64F7051SFJ20V Datasheet, PDF (268/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 10 Advanced Timer Unit (ATU)
Bit 6—Input Capture/Compare-Match Flag (IMF4D): Status flag that indicates GR4D input
capture or compare-match.
Bit 6:
IMF4D
0
1
Description
[Clearing condition])
(Initial value)
When IMF4D is read while set to 1, then 0 is written in IMF4D
[Setting conditions]
• When the TCNT4 value is transferred to GR4D by an input capture signal while
GR4D is functioning as an input capture register
• When TCNT4 = GR4D while GR4D is functioning as an output compare register
Bit 5—Input Capture/Compare-Match Flag (IMF4C): Status flag that indicates GR4C input
capture or compare-match.
Bit 5:
IMF4C
0
1
Description
[Clearing condition]
(Initial value)
When IMF4C is read while set to 1, then 0 is written in IMF4C
[Setting conditions]
• When the TCNT4 value is transferred to GR4C by an input capture signal while
GR4C is functioning as an input capture register
• When TCNT4 = GR4C while GR4C is functioning as an output compare register
Bit 4—Input Capture/Compare-Match Flag (IMF4B): Status flag that indicates GR4B input
capture or compare-match.
Bit 4:
IMF4B
0
1
Description
[Clearing condition]
(Initial value)
When IMF4B is read while set to 1, then 0 is written in IMF4B
[Setting conditions]
• When the TCNT4 value is transferred to GR4B by an input capture signal while
GR4B is functioning as an input capture register
• When TCNT4 = GR4B while GR4B is functioning as an output compare register
Rev. 5.00 Jan 06, 2006 page 246 of 818
REJ09B0273-0500