HD64F7051SFJ20V Datasheet, PDF (297/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 10 Advanced Timer Unit (ATU)
TCNT0 is initialized to H'00000000 by a power-on reset, and in hardware standby mode and
software standby mode.
Free-Running Counters 1 to 5 (TCNT1 to TCNT5): Free-running counters 1 to 5 (TCNT1 to
TCNT5) are 16-bit readable/writable registers that count on an input clock. The input clock is
selected with prescaler register 1 (PSCR1) and the timer control register (TCR).
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCNT3 to TCNT5 can be cleared to H'0000 by a compare-match with the corresponding general
register (GR) or input capture (counter clear function).
When one of counters TCNT1 to TCNT5 overflows (from H'FFFF to H'0000), the overflow flag
(OVF) for the corresponding channel in the timer status register (TSR) is set to 1.
TCNT1 to TCNT5 are connected to the CPU via an internal 16-bit bus, and can only be accessed
by a word read or write.
TCNT1 to TCNT5 are initialized to H'0000 by a power-on reset, and in hardware standby mode
and software standby mode.
Free-Running Counters 6 to 9 (TCNT6 to TCNT9): Free-running counters 6 to 9 (TCNT6 to
TCNT9) are 16-bit readable/writable registers that count on an input clock. The input clock is
selected with prescaler register 1 (PSCR1) and the timer control register (TCR).
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCNT6 to TCNT9 are connected to the CPU via an internal 16-bit bus, and can only be accessed
by a word read or write.
TCNT6 to TCNT9 are initialized to H'0001 by a power-on reset, and in hardware standby mode
and software standby mode.
Rev. 5.00 Jan 06, 2006 page 275 of 818
REJ09B0273-0500