HD64F7051SFJ20V Datasheet, PDF (815/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Appendix A On-Chip Supporting Module Registers
Timer Counter (TCNT)
H'FFFF8611
8
WDT
Bit: 7
6
5
4
3
2
1
0
Bit name:
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
7–0
(Count value)
Description
Input count clock value
Reset Control/Status Register
(RSTCSR)
H'FFFF8613
Bit: 7
6
5
4
3
Bit name: WOVF RSTE
—
—
—
Initial value: 0
0
0
0
1
R/W: R/(W)* R/W
R
R
R
Note: * Only 0 can be written in bit 7 to clear the flag.
8
2
1
—
—
1
1
R
R
WDT
0
—
1
R
Bit
Bit Name
Value Description
7
Watchdog timer 0
No TCNT overflow in watchdog timer mode (Initial value)
overflow flag
(WOVF)
[Clearing condition]
Read WOVF when WOVF =1, then write 0 in WOVF
1
TCNT overflow in watchdog timer mode
6
Reset enable
0
No internal reset when TCNT overflows (Initial value)
(RSTE)
1
Internal reset when TCNT overflows
Note: The SH7050 chip is not reset internally, but TCNT and TCSR are reset in the watchdog
timer.
Rev. 5.00 Jan 06, 2006 page 793 of 818
REJ09B0273-0500