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HD64F7051SFJ20V Datasheet, PDF (106/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC | |||
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Section 6 Interrupt Controller (INTC)
Interrupt Source
SCI1
ERI1
RXI1
TXI1
TEI1
SCI2
ERI2
RXI2
TXI2
TEI2
WDT
ITI
Interrupt Vector
Vector Table
Vector Address
No. Offset
Interrupt
Priority
(Initial
Value)
Corre-
sponding
IPR (Bits)
Priority
within IPR
Setting Default
Range Priority
156 H'00000270 to 0 to 15 (0) IPRH
â 1 High
H'00000273
(11â8)
â
157 H'00000274 to
2
H'00000277
158 H'00000278 to
3
H'0000027B
159 H'0000027C to
H'0000027F
â4
160 H'00000280 to 0 to 15 (0) IPRH
H'00000283
(7â4)
â1
161 H'00000284 to
2
H'00000287
162 H'00000288 to
3
H'0000028B
163 H'0000028C to
H'0000028F
164 H'00000290 to 0 to 15 (0) IPRH
H'00000293
(3â0)
â4
â
â
Low
6.3 Description of Registers
6.3.1 Interrupt Priority Registers AâH (IPRAâIPRH)
Interrupt priority registers AâH (IPRAâIPRH) are 16-bit readable/writable registers that set
priority levels from 0 to 15 for IRQ interrupts and on-chip peripheral module interrupts.
Correspondence between interrupt request sources and each of the IPRAâIPRH bits is shown in
table 6.4.
Rev. 5.00 Jan 06, 2006 page 84 of 818
REJ09B0273-0500
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